FIG. 1 illustrates a prior art BEMF system 100 having an A1 gain amplifier 110 of a Voice Coil Motor (VCM) 120 BEMF monitor in HDD servo IC.
In gain calibration mode, the VCM motor 120 is made still so its BEMF voltage is zero. Meanwhile, about 100 mA current is forced flowing through VCM motor and sense resistor Rs. The voltage drop on the sense resistor Rs is amplified by a digital programmable gain amplifier A1, and the A1 gain output is cancelled out with VCM voltage at A2 gain stage 130. Make A2 output zero by digitally changing A1 gain, A1 amplifier 110 gain is digitally calibrated to be equal to a ratio of motor resistance RVCM and sense resistance RSNS, that is,
      A    ⁢                  ⁢    1    ⁢    Gain    =                    R        VCM                    R        SNS              .  
In BEMF normal operation mode while VCM BEMF voltage presents, the current-resistance-product item of Rs is gained up by the calibrated A1 gain and is subtracted from the voltage across the VCM at A2 stage, that is,VA2OUT=VVCM−VA1OUT=(VVCM—BEMF+I×RVCM)−IVCM×RSNS×A1Gain=VVCM—BEMF  Equation (1)As shown in Equation (1), A2 amplifier 130 output is an estimation of VCM motor BEMF voltage. In modern HDD servo IC circuits, a 13-bit DAC is used for A1 programmable gain stage 110 to achieve required mV-level BEMF voltage measurement accuracy.
FIGS. 2A and 2B illustrate two prior art Programmable Gain Amplifier (PGA) approaches to BEMF monitor gain calibration of A1 gain 110. In FIG. 2A, switches of a first prior art PGA 200 performing gain programmability are tied to an operational amplifier's (OPA's) negative input node, and the switch on-state resistance Rds,on does not contribute to PGA gain error, because of an infinite impedance, thus zero input bias current to the inputs 211 and 212 of CMOS OPA.
However, the scheme of the PGA 200 also has a disadvantage. The gain is not linear to resistance increment/decrement which is linearly coded by switches S0-S(N). For example, in FIG. 2A, suppose N=63 (i.e., 64 switches/resistors in total) and the resistance between every node tapped out by switches are evenly equal to a given resistance R. When the digital input changes from code X=‘00H’ (switch S0 is turned on and all others are off) to X=‘01H’ (switch S1 is turned on and all others are off) and then to X=‘02H’ (switch S2 is turned on and all others are off), the PGA 200 gain, which is Rf/Rin, moves from 63 to 62/2 then to 61/3 which are non-linear gain steps. In other words, the PGA 200 does not have a linear transfer function although the digital code linearly changes. This lack of linearity does not meet system level requirements for typical servo systems.
In FIG. 2B, an alternative prior art PGA 250 of the A1 gain 110, the input resistance Rin between input Vin and the OPA negative input node is fixed, and the feedback resistance Rf is linearly coded by switches. As a result, the gain of the PGA 250 of an A1 PGA 110 is a linear function of the linearly coded resistance. For example, when digital code X=“00H” (switch S1 is turned on and all other switches are off) moves to X=“01H” (S2 is turned on and all others are off) then to X=“02H” (switch S3 is turned and all others are off) and finally moves to X=“3FH” (switch S(64) is turned on and all others are off), the gain Rf/Rin changes from to
      R    +          R                        S          ⁢                                          ⁢          1                ,        on                  R    in  to
                    2        ⁢        R            +              R                              S            ⁢                                                  ⁢            2                    ,          on                            R      in        ⁢          ⁢  then  ⁢          ⁢  to  ⁢          ⁢                    3        ⁢        R            +              R                              S            ⁢                                                  ⁢            3                    ,          on                            R      in        ⁢          ⁢  and  ⁢          ⁢  finally  ⁢          ⁢                              64          ⁢          R                +                  R                                    S              ⁢                                                          ⁢              64                        ,            on                                      R        in              .  The A1 gain is linear to the digital code change only when the switch on-state resistances are ideally zero.
Disadvantageously, however, in the prior art PGA 250 of FIG. 2B, the switch on-state resistances S1-SN, are in the signal path and they contribute to the amplifier gain error, unlike the prior art PGA 200. Furthermore, the switch resistances S(1)-S(N) and the poly resistors R(N) that create the gain for the PGA 250 have different temperature coefficients and voltage coefficients, and it can traverse into gain error over temperature variation and over voltage signal excursion during the operation.
Moreover, to succeed in high-volume product business such as HDDs, it is important to decrease circuit element counts and silicon area, for such reasons as saving cost of the IC controlling the HDD servo mechanism. In the discussed prior art PGAs, implementing single-ladder architecture of 13-bit programmable gain needs 213=8192 count of resistors and switches. This is unacceptable for most high-volume HDD servo IC applications.
FIG. 3 shows a prior art dual ladder DAC, with NMOS resistors used in the fine ladder forming a 13 bit programmable PGA. FIG. 3 illustrates a prior art dual-ladder architecture of 6+7, that is, implementing 6-bit in a coarse ladder and 7-bit in a fine ladder. This avoids the large number of switches and resistors used in either the PGA 200 or the PGA 250. The circuit complexity is reduced to 26+27=192 count of switches and resistors, which is about 43 times less complex in terms of used switches/resistors, compared to the single-ladder architecture of 13 bit resolution.
In the dual-ladder DAC architecture 300 of the A1 gain 110, to minimize DNL/INL error over process and temperature variations, (1) The resistance of on-state switch 321 and 322 between a coarse ladder 310 and a fine ladder 320 are considered as one unit of the fine ladder 320; (2) MOS resistors 323, 324, 325, 326 are used in the fine ladder 320, where a MOS resistor is defined as a MOS device working in deep triode region. Therefore, all the units along the fine ladder are same type of elements and they match with each other very well (over temperature and process variations) and the DAC DNL/INL performance is improved and silicon area is reduced.
However, a trade-off exists regards PGA 300 performance and the ratio between the fine ladder 320 total resistance N×RFL (where N is fine ladder 320 MOS resistor count) and the coarse ladder 310 unit resistance RCL, which is chosen to shunt with the fine ladder 320 for a specific input digital code. If ratio (N×RFL)/RCL is smaller than a certain value, a “shunt effect” degrades the DAC DNL/INL performance. This is because when the fine ladder 320 is switched and shunted to a specific coarse ladder resistor R1, the effective resistance of the shunted unit is relatively less than it used to be. In implementations, the error caused by the shunt effect
  1  -                    R        CL            //              (                  NR          FL                )                    R      CL      should be less than 0.5LSB. To reach the goal, RFL should be designed larger than a specific value. On the other hand, if ratio (N×RFL)/RCL is too large and over a certain threshold, the nominal current flowing through the fine ladder 320 is so small that it is conquered by the current leakage in the fine ladder 320.
In PGA 300, if equal resistances are used in the coarse ladder 310, the resulting programmable gain is not linear to the digital code as illustrated as line 330. To obtain the linear gain as line 331, the resistances in the coarse ladder 310 have to be carefully computed and they must not be equal.
As shown in FIG. 4 of a prior art PGA 400 and as understood and discovered by the present inventors, the fine ladder 420 nominal current is mostly leaked away locally at the back gate parasitic p-n junction diodes 424 and 425 in MOS resistors 421, back gate parasitic p-n junction diodes 426 and 427 in MOS resistor 422 and so on, as well as back gate parasitic p-n junction of switches 431, 432 and so on, all associated with the fine ladder 420. When ratio (N×RFL)/RCL is too large and the nominal current flowing through fine ladder 420 is small and comparable to leakage current, the net current goes through fine ladder MOS resistor channel notably decreases due to local MOS back gate leakage. That is, Ids1>Ids2>Ids3>Ids4 and so on until to some point, the MOS channel current is completely conquered by local leakage current and become zero. After that, the local leakage current is provided by a current coming from a reversed direction. Thus the net current direction flowing through the MOS resistor channel on the right end of the fine ladder 420, for example devices 426 and 427, are reversed to what it is supposed to be. The “leakage effect” causes the net current flowing through the prior art fine ladder 420 is not maintained in a consistent direction, therefore the voltage potential along the fine ladder does not monotonically decreases and it produces unacceptable non-monotonic gain scallop.
As understood by the present inventors, to achieve 13 bit resolution/linearity and minimize silicon area consumption, which is important to high volume HDD servo products, the error due to ‘shunt effect’ needs to be less than 0.5LSB, thus MOS resistors are used in the DAC fine ladder 420 and its resistances are designed to be much larger than the coarse ladder 410 unit resistance, that is, a large ratio (N×RFL)/RCL. An undesired side-effect, however, is that the nominal current of the fine ladder 420, which is a ratio RCL/(N×RFL+RCL) of the total current from Vin to Vout of the PGA stage, become extremely small. It is comparable to or even conquered by the back gate current leakage of the fine ladder 420 MOS resistor 421, 422 . . . and DAC switches 431, 432 and so on. It causes non-linear scallop and damages 13 bit resolution/linearity performance, especially when the voltage input to the A1 gain stage is small and therefore the nominal current flowing through fine ladder is very small.
Therefore, there is a need in the art as understood by the present inventors to address a design challenge is to balance between the “shunt effect” and the “leakage effect” and remove the non-monotonic scallop, wherein resistance in the coarse ladder is unevenly set to achieve linear coded programmable gain.